A synchronous static random access memory (SRAM) is a type of integrated circuit memory that has latches for all inputs and outputs, good drive capability, and a self timed write cycle, all on a single monolithic integrated circuit. A synchronous SRAM is typically used as a high speed cache in a data processing system. When being used as a cache, the synchronous SRAM is under the control of a single system clock. The synchronous SRAM has several advantages over an asynchronous SRAM. First, the synchronous SRAM generally requires fewer external logic chips. Second, the synchronous SRAM can operate at higher system speeds than a comparable asynchronous memory. However, as the synchronous SRAM is required to operate at higher system clock frequencies, timing specifications become increasingly more difficult to meet.
In today's synchronous SRAMs, a write cycle may be accomplished in less than one clock cycle. A write pulse is generated in order to establish a window for the write cycle to occur. During the write pulse, a relatively large differential signal on the bit lines over-writes the contents of a selected memory cell. At the end of the write cycle, bit line equalization causes the voltages on the bit line pair to be close enough so that data is not overwritten and that the correct data can be sensed quickly during a following read cycle. If the bit lines are not equalized fast enough, incorrect data may be written in the selected memory cell on the next read cycle.
The write signal must be of sufficient duration to allow data to be written into a selected memory cell. Typically, the write pulse is dependent on the frequency and the duty cycle of the system clock signal. The write pulse is initiated on the rising edge of the clock signal and the duration of the write pulse is determined by the duty cycle of the clock signal. At very high clock frequencies, or very short duty cycles (clock high time), there may not be enough time to successfully write data to a selected memory cell and then equalize the bit lines. For example, a system clock frequency of 125 megahertz provides a clock cycle of only 8 nanoseconds. For a 50% duty cycle, only 4 nanoseconds are available in which to accomplish a write cycle. A minor fluctuation in the frequency or duty cycle of the clock signal may cause incorrect data to be written into the memory.